This invention relates, in general, to semiconductor memories, and more particularly, to ferro-electric memory architectures.
A ferro-electric memory (FeRAM) is a non-volatile memory. It is useful for applications requiring data retention when power is removed from the memory. Both read and write operations are performed to a FeRAM. FeRAM read and write cycle times are within a range of 200 to 1000 nanoseconds for a 4096 bit memory. The memory size and memory architecture affect the read and write access times of a FeRAM. EEPROMs and FLASH EEPROMs are well known non-volatile memories that compete with ferro-electric memories.
The non-volatility of a ferro-electric memory is due to the bistable characteristic of a ferro-electric memory cell. Two types of memory cells are used, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell increases density but is less immune to noise and process variations, and requires a voltage reference for determining a stored memory state. The dual capacitor memory cell stores complementary signals allowing differential sampling of the stored information and is stable.
A dual capacitor ferro-electric memory cell in a memory array couples to a BIT and a BITBAR line that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferro-electric memory cell comprises two transistors and two ferro-electric capacitors. A first transistor couples between the BIT line and a first capacitor. A second transistor couples between the BITBAR line and a second capacitor. The first and second capacitors have a common terminal or plate to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors of the dual capacitor ferro-electric memory cell are enabled to couple the capacitors to the complementary logic levels on the BIT line and the BITBAR line corresponding to a logic state to be stored in memory. The common terminal of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell to one of the two logic states.
In a read operation, the first and second transistors of the dual capacitor memory cell are enabled to couple the information stored on the first and second capacitors to the BIT line and the BITBAR line. A differential signal is generated across the BIT line and the BITBAR line by the dual capacitor memory cell. The differential signal is sensed by a sense amplifier which provides a signal corresponding to the logic level stored in memory. A characteristic of a ferro-electric memory is that a read operation is destructive in some applications. The data in a memory cell must be rewritten back to the memory cell after the read operation is completed.
A memory cell of a ferro-electric memory is limited to a finite number read and write operations before the memory cell becomes unreliable. The number of operations that can be performed on a ferro-electric memory is known as the endurance of a memory. The endurance is an important factor in many applications that require a nonvolatile memory. Other factors such as memory size, memory speed, and power dissipation also play a role in determining if a ferro-electric memory is viable in the memory market.
It would be of great benefit if a ferro-electric memory could be provided that has increased endurance, higher speed, increased density, and dissipates less power.